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1 www.semtech.com sc1486a complete ddr1/2/3 power supply controller power management revision: september 20, 2006 description features applications typical application circuit the sc1486a is a dual output constant on-time synchronous buck pwm controller optimized for cost effective mobile ddr1, ddr2 and ddr3 applications. features include high efficiency, a fast dynamic response with no minimum on time, a refin input and a buffered refout pin capable of sourcing 3ma. the excellent transient response means that sc1486a based solutions will require less output capacitance than competing fixed frequency converters. the output voltage of the first controller can be adjusted from 0.5v to vcca. in ddr1 applications, this voltage is set to 2.5 volts, and in ddr2, 1.8v. a resistor divider from this supply is used to drive the refin pin of the second controller. a unity gain buffer drives the refout pin to the same potential as refin. the second controller regulates its output to refout. two frequency setting resistors set the on-time for each buck controller. the frequency can thus be tailored to minimize crosstalk. the integrated gate drivers feature adaptive shoot-through protection and soft switching, requiring no gate resistors for the top mosfet. additional features include cycle- by-cycle current limit, digital soft-start, over-voltage and under-voltage protection, and a power good output for each controller. ? notebook computers ? cpu i/o supplies ? handheld terminals and pdas ? 1% dc accuracy ? compatible with ddr1, ddr2 and ddr3 memory power requirements ? constant on-time for fast dynamic response ? vbat range = 1.8v ? 25v ? dc current sense using low-side rds(on) sensing or sense resistor ? integrated reference buffer for vtt ? low power s3 state with high-z vtt ? resistor programmable on-time ? cycle-by-cycle current limit ? digital soft-start ? psave option for vddq ? over-voltage/under-voltage fault protection ? <20a shutdown current ? low quiescent power dissipation ? two power good indicators ? separate enable for each switcher ? integrated gate drivers with soft switching - no gate resistors required ? efficiency >90% ? 28 lead tssop (lead-free available, fully weee and rohs compliant) d1 l1 r1 rton1 c8 10uf c13 1uf c4 1uf pgood c5 1nf vtt vddq c1 0.1uf vddq 5vsus 5vrun vssa2 vbat r5 c2 10uf c12 100nf vbat q1 c10 1uf r6 0r vddq vssa2 r8 10k r9 10r 5vsus r3 vssa1 pgood r7 q3 vssa1 vbat 5vsus l2 q2 q4 r2 10r vbat + c3 5vsus r14 0r r10 rton2 r4 r12 10r u1 sc1486a 22 23 24 25 26 27 28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 en/psv1 ton1 vout1 vcca1 fb1 pgd1 vssa1 pgnd1 dl1 vddp1 ilim1 lx1 dh1 bst1 refin ton2 refout vcca2 fb2 pgd2 vssa2 pgnd2 dl2 vddp2 ilim2 lx2 dh2 bst2 vtt r11 d2 + c9 c6 1uf c11 1nf refout r15 10k c7 0.1uf r13 c14 1uf
2 ? 2006 semtech corp. www.semtech.com sc1486a power management absolute maximum ratings electrical characteristics test conditions: v bat = 15v, en/psv1 = 5v, refin=1.25v, vcca1 = vddp1 = vcca2 =vddp2= 5.0v, v vddq = 2.5, v vtt = 1.25, r ton1 = 1m, r ton2 = 1m r e t e m a r a ps n o i t i d n o cc 5 2c 5 2 1 o t c 0 4 -s t i n u n i mp y tx a mn i mx a m s e i l p p u s t u p n i 2 a c c v , 1 a c c v 0 . 55 . 45 . 5v 2 p d d v , 1 p d d v 0 . 55 . 45 . 5v d l o h s e r h t e g a t l o v r e d n u 2 p d d vg n i l l a f 2 p d d v5 . 3v s i s e r e t s y h e g a t l o v r e d n u 2 p d d v 0 5 2v m t n e r r u c g n i t a r e p o 2 p d d v , 1 p d d vi , t n i o p n o i t a l u g e r > b f d a o l a 0 =0 70 5 1a t n e r r u c g n i t a r e p o 2 a c c v , 1 a c c vi , t n i o p n o i t a l u g e r > b f d a o l a 0 =0 0 70 0 1 1a t n e r r u c y b d n a t s 2 a c c vv u 2 p d d v < 2 p d d v t u o f e r n o d a o l o n , d l o h s e r h t 5 2 1a t n e r r u c g n i t a r e p o 2 n o t , 1 n o tr n o t m 1 =5 1a t n e r r u c s a i b n i f e r5 2 . 1 = n i f e r1a exceeding the specifications below may result in permanent damage to the device, or device malfunction. operation outside of th e parameters specified in the electrical characteristics section is not implied. r e t e m a r a p l o b m y sm u m i x a ms t i n u 2 a s s v o t 2 n o t , 1 a s s v o t 1 n o t 0 . 5 2 + o t 3 . 0 -v 2 d n g p o t 2 t s b , 2 h d d n a 1 d n g p o t 1 t s b , 1 h d 0 . 0 3 + o t 3 . 0 -v 2 d n g p o t 2 x l d n a 1 d n g p o t 1 x l 0 . 5 2 + o t 0 . 2 -v 2 d n g p o t 2 a s s v d n a , 1 d n g p o t 1 a s s v 3 . 0 + o t 3 . 0 -v 2 x l o t 2 t s b d n a 1 x l o t 1 t s b 0 . 6 + o t 3 . 0 -v 2 d n g p o t 2 p d d v , 2 m i l i , 2 l d d n a 1 d n g p o t 1 p d d v , 1 m i l i , 1 l d 0 . 6 + o t 3 . 0 -v 1 a s s v o t 1 t u o v , 1 a c c v , 1 d o o g p , 1 b f , 1 v s p / n e 0 . 6 + o t 3 . 0 -v 2 a s s v o t t u o f e r , n i f e r , 2 a c c v , 2 d o o g p , 2 b f 0 . 6 + o t 3 . 0 -v 1 t u o v , 1 d o o g p , 1 b f , 1 v s p / n e o t 1 a c c v 0 . 6 + o t 3 . 0 -v t u o f e r , n i f e r , 2 d o o g p , 2 b f o t 2 a c c v 0 . 6 + o t 3 . 0 -v t n e i b m a o t n o i t c n u j e c n a t s i s e r l a m r e h t ) 5 ( a j 0 7w / c e g n a r e r u t a r e p m e t n o i t c n u j g n i t a r e p o t j 5 2 1 + o t 0 4 -c e g n a r e r u t a r e p m e t e g a r o t s t g t s 0 5 1 + o t 5 6 -c . c e s 0 1 ) g n i r e d l o s ( e r u t a r e p m e t d a e l t d a e l 0 0 3c
3 ? 2006 semtech corp. www.semtech.com sc1486a power management electrical characteristics (cont.) r e t e m a r a ps n o i t i d n o cc 5 2c 5 2 1 o t c 0 4 -s t i n u n i mp y tx a mn i mx a m ) . t n o c ( s e i l p p u s t u p n i t n e r r u c n w o d t u h sv 0 = 1 v s p / n e5 -0 1 -a 2 a c c v , 1 a c c v50 1a 1 p d d v , 2 n o t , 1 n o t01a r e l l o r t n o c d l o h s e r h t r o t a r a p m o c r o r r e ) d l o h s e r h t n o n r u t 1 b f ( v 5 . 5 o t v 5 . 4 = a c c v0 0 5 . 0% 1 -% 1 +v e g n a r e g a t l o v t u p t u o q d d v 5 . 0a c c vv y t i l i b a p a c e c r u o s t u o f e r 3a m y c a r u c c a c d t u o f e r5 2 . 1 = n i f e r , d a o l o n4 2 . 16 2 . 18 3 2 . 12 6 2 . 1v d l o h s e r h t r o t a r a p m o c r o r r e ) d l o h s e r h t n o n r u t 2 b f ( v 5 . 5 o t v 5 . 4 = a c c v t u o f e rt u o f e r v m 0 1 - t u o f e r v m 0 1 + v v 5 . 2 = t a b v , e m i t - n or n o t m 1 = ? v 5 2 . 1 = t u o v ,1 6 7 17 9 4 15 2 0 2s n r n o t k 0 0 5 = ? v 5 2 . 1 = t u o v ,6 3 96 9 76 7 0 1s n e m i t f f o m u m i n i m 0 0 40 5 5s n e c n a t s i s e r t u p n i t u o v ) r e l l o r t n o c q d d v ( 0 0 5k ? t n e r r u c s a i b t u p n i 1 b f 0 . 1 -0 . 1 +a t n e r r u c s a i b t u p n i 2 b f 5 . 2a g n i s n e s t n e r r u c - r e v o t n e r r u c e c r u o s m i l ih g i h l d0 191 1a t e s f f o r o t a r a p m o c t n e r r u cm i l i - d n g p0 1 -0 1 +v m e v a s p d l o h s e r h t g n i s s o r c - o r e zx l - d n g p v 5 = 1 v s p / n e 5v m n o i t c e t o r p t l u a f ) e v i t i s o p ( t i m i l t n e r r u c ) 2 ( ) x l - d n g p ( r m i l i k 5 = ? 0 55 35 6v m r m i l i k 0 1 = ? 0 0 10 80 2 1v m r m i l i k 0 2 = ? 0 0 20 7 10 3 2v m ) e v i t a g e n ( t i m i l t n e r r u c ) x l - d n g p ( 5 2 1 -0 6 1 -0 9 -v m test conditions: v bat = 15v, en/psv1 = 5v, refin=1.25v, vcca1 = vddp1 = vcca2 =vddp2= 5.0v, v vddq = 2.5, v vtt = 1.25, r ton1 = 1m, r ton2 = 1m
4 ? 2006 semtech corp. www.semtech.com sc1486a power management electrical characteristics (cont.) r e t e m a r a ps n o i t i d n o cc 5 2c 5 2 1 o t c 0 4 -s t i n u n i mp y tx a mn i mx a m ) . t n o c ( n o i t c e t o r p t l u a f t l u a f e g a t l o v - r e d n u t u p t u o - q d d v. f e r l a n r e t n i o t t c e p s e r h t i w0 3 -0 4 -5 2 -% t l u a f e g a t l o v - r e d n u t u p t u o - t t vt u o f e r o t t c e p s e r h t i w0 2 -8 2 -5 1 -% t l u a f e g a t l o v - r e v o t u p t u o q d d v. f e r l a n r e t n i o t t c e p s e r h t i w0 1 +8 +2 1 +% t l u a f e g a t l o v - r e v o t u p t u o t t v 0 . 29 . 11 . 2v y a l e d t l u a f e g a t l o v - r e v od l o h s e r h t v o e v o b a d e c r o f b f5s e g a t l o v t u p t u o w o l d g pa m 1 k n i s4 . 0v t n e r r u c e g a k a e l d g pv 5 = d g p , n o i t a l u g e r n i b f1a d l o h s e r h t v u d g pl a n r e t n i o t t c e p s e r h t i w d n a q d d v r o f e c n e r e f e r t t v r o f t u o f e r 0 1 -5 1 -8 -% ) q d d v ( d l o h s e r h t v o d g p. f e r l a n r e t n i o t t c e p s e r h t i w0 1 +8 +2 1 +% ) t t v ( d l o h s e r h t v o d g p 0 . 29 . 11 . 2v y a l e d t l u a f d g pw o d n i w d g p e d i s t u o d e c r o f b f5s e g a t l o v r e d n u 2 a c c v , 1 a c c v) s i s e r e t s y h v m 0 0 1 ( g n i l l a f0 . 47 . 33 . 4v t u o k c o l e r u t a r e p m e t r e v os i s e r e t s y h c 0 15 6 1c s t u p t u o / s t u p n i e g a t l o v w o l t u p n i c i g o lw o l 1 v s p / n e2 . 1v e g a t l o v h g i h t u p n i c i g o l) g n i t a o l f ( w o l v s p , h g i h n e0 . 2v e g a t l o v h g i h t u p n i c i g o lh g i h 1 v s p / n e1 . 3v d l o h s e r h t n e n i f e rg n i s i r n i f e r0 5 . 00 6 . 0v s i s e r e t s y h n e n i f e r 0 3v m e c n a t s i s e r t u p n i 1 v s p / n e1 a c c v o t p u l l u p r5 . 1m ? 1 a s s v o t n w o d l l u p r0 . 1 t r a t s t f o s e m i t p m a r t r a t s - t f o s, h g i h 1 d g p o t h g i h 1 v s p / n e h g i h 2 d g p o t h g i h n i f e r 0 4 4s k l c ) 3 ( e m i t k n a l b e g a t l o v - r e d n u, h g i h v u o t h g i h 1 v s p / n e h g i h v u o t h g i h n i f e r 0 4 4s k l c ) 3 ( test conditions: v bat = 15v, en/psv1 = 5v, refin=1.25v, vcca1 = vddp1 = vcca2 =vddp2= 5.0v, v vddq = 2.5, v vtt = 1.25, r ton1 = 1m, r ton2 = 1m
5 ? 2006 semtech corp. www.semtech.com sc1486a power management notes: (1) the output voltage will have a dc regulation level higher than the error-comparator threshold by 50% of the ripple voltage. (2) using a current sense resistor, this measurement relates to pgnd minus the voltage of the source on the low-side mosfet. these values guaranteed by the ilim source current and current comparator offset tests. (3) clks = switching cycles. (4) guaranteed by design. see shoot-through delay timing diagram below. (5) measured in accordance with jesd51-1, jesd51-2 and jesd51-7. (6) this device is esd sensitive. use of standard esd handling precautions is required. electrical characteristics (cont.) r e t e m a r a ps n o i t i d n o cc 5 2c 5 2 1 o t c 0 4 -s t i n u n i mp y tx a mn i mx a m s r e v i r d e t a g y a l e d h g u o r h t - t o o h s ) 4 ( g n i s i r l d r o h d0 3s n e c n a t s i s e r n w o d - l l u p l dw o l l d8 . 06 . 1 ? t n e r r u c k n i s l dv 5 . 2 = l d1 . 3 e c n a t s i s e r p u - l l u p l dh g i h l d24 ? t n e r r u c e c r u o s l dv 5 . 2 = l d3 . 1a e c n a t s i s e r n w o d - l l u p h dv 5 = x l - t s b , w o l h d24 ? e c n a t s i s e r p u - l l u p h dv 5 = x l - t s b , h g i h h d24 ? t n e r r u c e c r u o s / k n i s h dv 5 . 2 = l d3 . 1a test conditions: v bat = 15v, en/psv1 = 5v, refin=1.25v, vcca1 = vddp1 = vcca2 =vddp2= 5.0v, v vddq = 2.5, v vtt = 1.25, r ton1 = 1m, r ton2 = 1m shoot-through delay timing diagram tplhdl tplhdh lx dl dl dh
6 ? 2006 semtech corp. www.semtech.com sc1486a power management pin configuration (tssop-28) e c i v e de g a k c a p ) 1 ( r t s t i a 6 8 4 1 c s8 2 - p o s s t t r t s t i a 6 8 4 1 c s ) 2 ( 8 2 - p o s s t b v e a 6 8 4 1 c s ) 3 ( d r a o b n o i t a u l a v e ordering information top view # n i pe m a n n i pn o i t c n u f n i p 11 d n g p. d n u o r g r e w o p 21 l d. h c t i w s t e f s o m e d i s w o l e h t r o f t u p t u o e v i r d e t a g 31 p d d v o t r o t i c a p a c c i m a r e c f 1 a h t i w n i p s i h t e l p u o c e d . s r e v i r d e t a g e h t r o f t u p n i e g a t l o v y l p p u s v 5 + . 1 d n g p 41 m i l i e c r u o s e h t r o g n i s n e s ) n o ( s d r r o f t e f s o m e d i s - w o l f o n i a r d o t t c e n n o c . n i p t u p n i t i m i l t n e r r u c . r o t s i s e r g n i s n e s d l o h s e r h t a h g u o r h t g n i s n e s r o t s i s e r r o f 51 x l . n o i t c e n n o c ) r o t c u d n i t u p t u o e h t d n a s t e f s o m m o t t o b d n a p o t f o n o i t c n u j ( e d o n e s a h p 61 h d. h c t i w s t e f s o m e d i s h g i h e h t r o f t u p t u o e v i r d e t a g 71 t s b. e v i r d e t a g e d i s h g i h e h t r o f n o i t c e n n o c r o t i c a p a c t s o o b 8n i f e r a . e g a t l o v s i h t s t e s 2 a s s v o t q d d v m o r f r e d i v i d r o t s i s e r m h o k 0 1 + m h o k 0 1 a . t u p n i e c n e r e f e r . d e d n e m m o c e r s i r o t i c a p a c r e t l i f t u p n i f 1 . 0 92 n o t t e f s o m p o t e h t t e s o t d n a , 2 n o t r , r o t s i s e r p u l l u p a h g u o r h t t a b v e s n e s o t d e s u s i n i p s i h t . 2 a s s v o t r o t i c a p a c c i m a r e c f n 1 a h t i w n i p s i h t s s a p y b . e m i t - n o 0 1t u o f e r m h o 0 1 s e i r e s a t c e n n o c . e g a t l o v s i h t o t s e t a l u g e r r e l l o r t n o c d n o c e s e h t . t u p t u o n i f e r d e r e f f u b . 2 a s s v o t n i p s i h t m o r f f 1 d n a 1 12 a c c v . 2 a s s v o t s u s v 5 m o r f r e t l i f c r f 1 / m h o 0 1 a e s u . y l p p u s g o l a n a e h t r o f t u p n i e g a t l o v y l p p u s 2 12 b f . r o t i c a p a c t u p t u o e h t t a t u p t u o e h t o t t c e n n o c . 2 t u p t u o r o f t u p n i k c a b d e e f 3 12 d g p ) s e l c y c 0 4 4 ( y a l e d e l c y c k c o l c d e x i f a r e t f a h g i h s e o g . t u p t u o s o m n n i a r d n e p o d o o g r e w o p . p u r e w o p g n i w o l l o f 4 12 a s s v t u p t u o r o f r o t i c a p a c t u p t u o f o m o t t o b o t t c e n n o c . 2 t u p t u o r o f y r t i u c r i c g o l a n a r o f e c n e r e f e r d n u o r g . 2 pin descriptions notes: (1) only available in tape and reel packaging. a reel contains 2500 devices. (2) lead-free option. this product is fully weee, rohs and j-std-020b compliant. (3) specify ddr, ddr2 or ddr3.
7 ? 2006 semtech corp. www.semtech.com sc1486a power management pin descriptions (cont) 5 12 d n g p. d n u o r g r e w o p 6 12 l d. h c t i w s t e f s o m e d i s w o l e h t r o f t u p t u o e v i r d e t a g 7 12 p d d v o t r o t i c a p a c c i m a r e c f 1 a h t i w n i p s i h t e l p u o c e d . s r e v i r d e t a g e h t r o f t u p n i e g a t l o v y l p p u s v 5 + . 2 d n g p 8 12 m i l i e c r u o s e h t r o g n i s n e s ) n o ( s d r r o f t e f s o m e d i s - w o l f o n i a r d o t t c e n n o c . n i p t u p n i t i m i l t n e r r u c . r o t s i s e r g n i s n e s d l o h s e r h t a h g u o r h t g n i s n e s r o t s i s e r r o f 9 12 x l . n o i t c e n n o c ) r o t c u d n i t u p t u o e h t d n a s t e f s o m m o t t o b d n a p o t f o n o i t c n u j ( e d o n e s a h p 0 22 h d. h c t i w s t e f s o m e d i s h g i h e h t r o f t u p t u o e v i r d e t a g 1 22 t s b. e v i r d e t a g e d i s h g i h e h t r o f n o i t c e n n o c r o t i c a p a c t s o o b 2 21 v s p / n e s i h t e l b a n e o t p u l l u p . t u p t u o s i h t n w o d t u h s o t 1 a s s v o t n w o d l l u p . n i p t u p n i e v a s r e w o p / e l b a n e n o i t c u d n o c s u o u n i t n o c e t a v i t c a d n a t u p t u o s i h t e l b a n e o t t a o l f . e d o m e v a s p e t a v i t c a d n a t u p t u o . r o t i c a p a c c i m a r e c f n 0 1 a h t i w 1 a s s v o t s s a p y b , d e t a o l f f i . ) m c c ( e d o m 3 21 n o t - n o t e f s o m p o t e h t t e s o t d n a , 1 n o t r , r o t s i s e r p u l l u p a h g u o r h t t a b v e s n e s o t d e s u s i n i p s i h t . 1 a s s v o t r o t i c a p a c c i m a r e c f n 1 a h t i w n i p s i h t s s a p y b . e m i t 4 21 t u o v . r o t i c a p a c t u p t u o e h t t a t u p t u o e h t o t t c e n n o c . 1 t u p t u o r o f t u p n i e s n e s e g a t l o v t u p t u o 5 21 a c c v . 1 a s s v o t s u s v 5 m o r f r e t l i f c r f 1 / m h o 0 1 a e s u . y l p p u s g o l a n a e h t r o f t u p n i e g a t l o v y l p p u s 6 21 b f e h t t e s o t 1 a s s v o t 1 t u o v m o r f c i e h t t a d e t a c o l r e d i v i d r o t s i s e r a o t t c e n n o c . t u p n i k c a b d e e f . 1 a c c v o t v 5 . 0 m o r f e g a t l o v t u p t u o 7 21 d g p ) s e l c y c 0 4 4 ( y a l e d e l c y c k c o l c d e x i f a r e t f a h g i h s e o g . t u p t u o s o m n n i a r d n e p o d o o g r e w o p . p u r e w o p g n i w o l l o f 8 21 a s s v t u p t u o f o m o t t o b o t t c e n n o c . 1 t u p t u o r o f y r t i u c r i c g o l a n a r o f e c n e r e f e r d n u o r g . 1 t u p t u o r o f r o t i c a p a c
8 ? 2006 semtech corp. www.semtech.com sc1486a power management block diagram figure 1 - sc1486a block diagram on fb2 (12) vcca2 (11) toff oc bst2 (21) logic pgd1 (27) refout (10) ref + 10% hi x3 fb1 (26) + - 1.5v ref zero i dh2 (20) fault vout1 (24) on control isense ref buffer lx2 (19) ton1 (23) monitor ov uv ref - 10% + - lo en/spv1 (22) oc vcca1 (25) + - ilim2 (18) vddp2 bst1 (7) zero i hi vddp2 (17) dh1 (6) dl2 (16) fault lx1 (5) por / ss ot ref - 30% uv pgnd2 (15) lo ilim1 (4) pwm off pwm ton2 (9) vddp1 (3) ot 2v isense ref - 20% control ton ton toff monitor logic ov dl1 (2) ref - 10% off refin (8) vssa2 (14) pgnd1 (1) por / ss pgd2 (13) vssa1 (28)
9 ? 2006 semtech corp. www.semtech.com sc1486a power management application information +5v bias supplies the sc1486a requires an external +5v bias supply in addition to the battery. if stand-alone capability is required, the +5v supply can be generated with an external linear regulator. to minimize channel to channel crosstalk, each controller has 4 supply pins, vddp, pgnd, vcca and vssa. to avoid interference between outputs, each controller has its own ground reference, vssa, which should be tied by a single trace to pgnd at the negative terminal of that controller?s output capacitor (see layout guidelines). all external components referenced to vssa in the schematic should be connected to the appropriate vssa trace. the supply decoupling capacitor for controller 1 should be tied between vcca1 and vssa1. likewise, the supply decoupling capacitor for controller 2 should be tied between vcca2 and vssa2. a 10 ? resistor should be used to decouple each vcca supply from the main vddp supplies. pgnd can then be a separate plane which is not used for routing traces. all pgnd connections are connected directly to the ground plane with special attention given to avoiding indirect connections which may create ground loops. as mentioned above, vssa1 and vssa2 must be connected to the pgnd plane at the negative terminal of their respective output capacitors only. the vddp1 and vddp2 inputs provide power to the upper and lower gate drivers. a decoupling capacitor for each supply is required. no series resistor between vddp and 5v is required. see layout guidelines for more details. pseudo-fixed frequency constant on-time pwm controller the pwm control architecture consists of a constant on- time, pseudo fixed frequency pwm controller (see figure 1, sc1486a block diagram). the output ripple voltage developed across the output filter capacitor?s esr provides the pwm ramp signal eliminating the need for a current sense resistor. the high-side switch on-time is determined by a one-shot whose period is directly proportional to output voltage and inversely proportional to input voltage. a second one-shot sets the minimum off-time which is typically 400ns. on-time one-shot (t on ) the on-time one-shot comparator has two inputs. one input looks at the output voltage, while the other input samples the input voltage and converts it to a current. this input voltage-proportional current is used to charge an internal on-time capacitor. the on-time is the time required for the voltage on this capacitor to charge from zero volts to vout, thereby making the on-time of the high-side switch directly proportional to output voltage and inversely proportional to input voltage. this implementation results in a nearly constant switching frequency without the need for a clock generator. for vout < 3.3v: ns 50 v v ) 10 x 37 r ( 10 x 3 . 3 t in out 3 ton 12 on + ? ? ? ? ? ? ? ? ? + ? = ? for 3.3v vout 5v: ns 50 v v ) 10 x 37 r ( 10 x 3 . 3 85 . 0 t in out 3 ton 12 on + ? ? ? ? ? ? ? ? ? + ? ? = ? r ton is a resistor connected from the input supply to the ton pin. due to the high impedance of this resistor, the ton pin should always be bypassed to vssa using a 1nf ceramic capacitor. enable & psave the en/psv pin enables the vddq (2.5v or 1.8v) supply. refin and vddp2 enable the vtt (1.25v or 0.9v) supply. the vtt and vddq supplies may be enabled independently, however it is usual to use a resistor divider from vddq to generate refin, so if vddq is not present, vtt will not be present. when en/psv1 is tied to vcca the vddq controller is enabled and power save will also be enabled. when the en/psv pin is tri-stated, an internal pull-up will activate the vddq controller and power save will be disabled. if psave is enabled, the sc1486a psave comparator will look for the inductor current to cross zero on eight consecutive switching cycles by comparing the phase node (lx) to pgnd. once observed, the controller will enter power save and turn off the low side mosfet when the current crosses zero. to improve light-load efficiency and add hysteresis, the on-time is increased by 50% in power save. the efficiency improvement at light-loads more than offsets the disadvantage of slightly higher output ripple. if the inductor current does not cross zero on any switching cycle, the controller will immediately exit power save. since the controller counts zero crossings, the converter can sink current as long as the current does not cross zero on eight consecutive cycles. this allows the output voltage to recover quickly in response to negative load steps even when psave is enabled.
10 ? 2006 semtech corp. www.semtech.com sc1486a power management application information (cont.) figure 3: valley current limiting the equation for the current limit threshold is as follows: a r r 10e i sense ilim 6 - limit ? = where (referring to figure 2) r ilim is r5 and r sense is the r ds(on) of q3. for resistor sensing, a sense resistor is placed between the source of q3 and pgnd. the current through the source sense resistor develops a voltage that opposes the voltage developed across r ilim . when the voltage developed across the r sense resistor reaches the voltage drop across r ilim , a positive over-current exists and the high side mosfet will not be allowed to turn on. when using an external sense resistor r sense is the resistance of the sense resistor. the current limit circuitry also protects against negative over-current (i.e. when the current is flowing from the load to pgnd through the inductor and bottom mosfet). in this case, when the bottom mosfet is turned on, the phase node, lx, will be higher than pgnd initially. the sc1486a monitors the voltage at lx, and if it is greater than a set threshold voltage of 140mv (nom.) the bottom mosfet is turned off. the device then waits for approximately 2s and then dl goes high for 300ns (typ.) once more to sense the current. this repeats until either the over-current condition goes away or the part out1 output voltage selection the output voltage is set by the feedback resistors r10 & r13 of figure 2 below. the internal reference is 1.5v, so the voltage at the feedback pin is multiplied by three to match the 1.5v reference. therefore the output can be set to a minimum of 0.5v. the equation for setting the output voltage is: 5 . 0 13 r 10 r 1 vout ? ? ? ? ? ? ? + = 5vsus 0402 c1 2n2/50v q2 irf7811av 1 2 3 4 5 6 7 8 s s s g d d d d sod 0402 7343 0603 0402 323 r5 13k3 c2 0u1/25v 0603 r3 1m r13 17k4 c10 0u1 d1 0402 r10 45k3 1210 + c14 330u/25m c20 1n 1.8v 0402 l1 2u4 5vsus c17 27p pgood1 vcca1 0402 r1 10r vcca1 0603 0603 vcca1 r7 0r 0402 c3 10u/25v u1 sc1486a 3 1 23 6 7 5 4 22 27 24 26 25 28 17 15 9 20 21 19 18 13 12 8 10 11 14 2 16 vddp1 pgnd1 ton1 dh1 bst1 lx1 ilim1 en/psv1 pgd1 vout1 fb1 vcca1 vssa1 vddp2 pgnd2 ton2 dh2 bst2 lx2 ilim2 pgd2 fb2 refin refout vcca2 vssa2 dl1 dl2 c4 10u/25v c21 1u ton1 c8 1u 0402 0402 7343 + c13 330u/25m pgd1 r14 470k q3 fds6676s 1 2 3 4 5 6 7 8 s s s g d d d d vssa1 0402 0402 1.8v, 10a pwr_src 1210 c12 0u1 figure 2: setting vddq output voltage current limit circuit current limiting of the sc1486a can be accomplished in two ways. the on-state resistance of the low-side mosfets can be used as the current sensing element or sense resistors in series with the low-side sources can be used if greater accuracy is desired. r ds(on) sensing is more efficient and less expensive. in both cases, the r ilim resistors between the ilim pin and lx pin set the over current threshold. this resistor r ilim is connected to a 10 a current source within the sc1486a which is turned on when the low side mosfet turns on. when the voltage drop across the sense resistor or low side mosfet equals the voltage across the rilim resisor, positive current limit will activate. the high side mosfet will not be turned on until the voltage drop across the sense element (resistor or mosfet) falls below the voltage across the r ilim resistor. in an extreme over- current situation, the top mosfet will never turn back on and eventually the part will latch off due to output undervoltage (see output undervoltage protection). the current sensing circuit actually regulates the inductor valley current (see figure 3). this means that if the current limit is set to 10a, the peak current through the inductor would be 10a plus the peak ripple current, and the average current through the inductor would be 10a plus 1/2 the peak-to-peak ripple current. the equations for setting the valley current and calculating the average current through the inductor are shown below: i limit i load i peak inductor curren t time valley current-limit threshold point
11 ? 2006 semtech corp. www.semtech.com sc1486a power management application information (cont.) current limit circuit (cont.) latches off due to output overvoltage (see output overvoltage protection). power good output each controller has its own power good output. power good is an open-drain output and requires a pull-up resistor. when vddq is 10% above or below its set volt- age, or vtt is 2v or 10% below refout, pgd for that output gets pulled low. it is held low until the output volt- age returns to within these limits. pgd is also held low during start-up and will not be allowed to transition high until soft start is over (440 switching cycles) and the out- put reaches 90% of its set voltage. there is a 5s delay built into the pgd circuitry to prevent false transitions. output overvoltage protection when vddq exceeds 10% of its set voltage or vtt exceeds 2v, the low side mosfet for that output is latched on. it stays latched on and the controller is latched off until reset (see below). there is a 5s delay built into the ov protection circuit to prevent false transitions. an ov fault in vtt will not affect vddq. an ov fault in vddq will shut down vtt if vddq is used to generate refin. note: to reset vddq from any fault, vcca1 or en/psv1 must be toggled. to reset vtt from a fault, vcca2 or refin must be toggled. output undervoltage protection when the output is 30% (20% for vtt) below its set volt- age the output is latched in a tri-stated condition. it stays latched and the controller is latched off until reset (see below). there is a 5s delay built into the uv protection circuit to prevent false transitions. a uv fault in vtt will not affect vddq. a uv fault in vddq will shut down vtt if vddq is used to generate refin. note: to reset vddq from any fault, vcca1 or en/psv1 must be toggled. to reset vtt from a fault, vcca2 or refin must be toggled. por, uvlo and softstart an internal power-on reset (por) occurs when vcca1 and vcca2 exceed 3v, resetting the fault latch and soft-start counter, and preparing the pwm for switching. vcca undervoltage lockout (uvlo) circuitry inhibits switching and forces the dl gate driver high until vcca rises above 4.2v. at this time the circuit will come out of uvlo and begin switching, and with the softstart circuit enabled, will progressively limit the output current (by limiting the current out of the ilim pin) over a predetermined time period of 440 switching cycles. the vtt switcher operates slightly differently in order to implement suspend to ram (s3) mode. vddp2 is used to enable the switcher. if refin is greater than ~0.5v and vddp2 is less than ~3.25v, refout will be present but the vtt switcher will be disabled (vtt = high-z). if refin is greater than ~0.5v and vddp2 is greater than ~3.25v both refout and the vtt switcher will be enabled. the ramp occurs in four steps: 1) 110 cycles at 25% ilim with double minimum off-time (for purposes of the on-time one-shot there is an internal positive offset of 120mv to vout during this period to aid in startup) 2) 110 cycles at 50% ilim with normal minimum off-time 3) 110 cycles at 75% ilim with normal minimum off-time 4) 110 cycles at 100% ilim with normal minimum off-time. at this point the output undervoltage and power good circuitry is enabled. there is 100mv of hysteresis built into the uvlo circuit and when vcca falls to 4.1v (nom.) the output drivers are shut down and tristated. mosfet gate drivers the dh and dl drivers are optimized for driving moderate-sized high-side, and larger low-side power mosfets. an adaptive dead-time circuit monitors the dl output and prevents the high-side mosfet from turning on until dl is fully off (below ~1v). conversely, it monitors the phase node, lx, to determine the state of the high side mosfet, and prevents the low-side mosfet from turning on until dh is fully off (lx below ~1v). be sure there is low resistance and low inductance between the dh and dl outputs to the gate of each mosfet. ddr reference buffer the reference buffer is capable of driving 3ma and sinking 25a. since the output is class a, if additional sinking is required an external pulldown resistor can be added. make sure that the ground side of this pulldown is tied to vssa2. as with most opamps, a small resistor is required when driving a capacitive load. to ensure stability use either a 10 ? resistor in series with a 1f capacitor or a 100 ? resistor in series with a 0.1f capacitor from refout to agnd2. since it is possible to have as much as 10f to 20f of capacitance at the memory socket or on-board the dimms, it is recommended that a 0 ? resistor is placed between refout and the dimm sockets. this allows the
12 ? 2006 semtech corp. www.semtech.com sc1486a power management addition of extra resistance between refout and the dimms to avoid spurious ovp at startup, which can occur if refout rises really slowly and vtt overshoots it. the extra resistance allows refout to rise faster, avoiding this issue. refin should also be filtered so that vddq ripple does not appear at the refin pin. if a resistor divider is used to create refin from vddq, then a 0.1f capacitor from refin to vssa2 will provide adequate filtering. dropout performance the output voltage adjust range for continuous- conduction operation is limited by the fixed 550ns (maximum) minimum off-time one-shot. for best dropout performance, use the slowest on-time setting of 200khz. when working with low input voltages, the duty-factor limit must be calculated using worst-case values for on and off times. the ic duty-factor limitation is given by: ) max ( off t ) min ( on t ) min ( on t duty + = be sure to include inductor resistance and mosfet on- state voltage drops when performing worst-case dropout duty-factor calculations. sc1486a system dc accuracy (vtt controller) two ic parameters effect system dc accuracy, the error comparator offset voltage, and the switching frequency variation with line and load. the sc1486a regulates to the refout voltage not the refin voltage. since ddr specifications are written with respect to refout, the offset of the reference buffer does not create a regulation error. the error comparator offset does not drift significantly with supply and temperature. thus, the error comparator contributes 1% or less to dc system inaccuracy. the on pulse in the sc1486a is calculated to give a pseudo fixed frequency. nevertheless, some frequency variation with line and load can be expected. this variation changes the output ripple voltage. because constant on regulators regulate to the valley of the output ripple, ? of the output ripple appears as a dc regulation error. for example, if refout=1.25v, then the valley of the output ripple will be 1.25v. if the ripple is 20mv with vin = 6v, then the dc output voltage will be 1.26v. if the ripple is 40mv with vin = 25v, then the dc output voltage will be 1.27v. 1486 system dc accuracy (vddq controller) two ic parameters affect system dc accuracy, the error comparator threshold voltage variation and the switching frequency variation with line and load. the error comparator threshold does not drift significantly with supply and temperature. thus, the error comparator contributes 1% or less to dc system inaccuracy. board components and layout also influence dc accuracy. the use of 1% feedback resistors contribute 1%. if tighter dc accuracy is required use 0.1% feedback resistors. the on pulse in the sc1486a is calculated to give a pseudo fixed frequency. nevertheless, some frequency variation with line and load can be expected. this variation changes the output ripple voltage. because constant on regulators regulate to the valley of the output ripple, ? of the output ripple appears as a dc regulation error. for example, if the feedback resistors are chosen to divide down the output by a factor of five, the valley of the output ripple will be 2.5v. if the ripple is 50mv with vin = 6v, then the measured dc output will be 2.525v. if the ripple increases to 80mv with vin = 25v, then the measured dc output will be 2.540v. the output inductor value may change with current. this will change the output ripple and thus the dc output voltage. it will not change the frequency. switching frequency variation with load can be minimized by choosing mosfets with lower r ds(on) . high r ds(on) mosfets will cause the switching frequency to increase as the load current increases. this will reduce the ripple and thus the dc output voltage. ddr supply selection the sc1486a can be configured so that vtt and vddq are generated directly from the battery. alternatively, the vtt supply can be generated from the vddq supply. since the battery configuration generally yields better efficiency and performance, the evaluation board is configured to generate both supplies from the battery. application information (cont.)
13 ? 2006 semtech corp. www.semtech.com sc1486a power management application information (cont.) design procedure prior to designing an output and making component selections, it is necessary to determine the input voltage range and the output voltage specifications. for purposes of demonstrating the procedure the vddq output for the schematic on page 17 will be designed. the maximum input voltage (v in(max) ) is determined by the highest ac adaptor voltage. the minimum input voltage (v in(min) ) is determined by the lowest battery voltage after accounting for voltage drops due to connectors, fuses and battery selector switches. for the purposes of this design example we will use a v in range of 7.5v to 20.5v. four parameters are needed for the output: 1) nominal output voltage, v out (for ddr2 this is 1.8v) 2) static (or dc) tolerance, tol st (for ddr2 this is +/-0.1v) 3) transient tolerance, tol tr and size of transient (for ddr2 this is undefined, so assume +/-8% for purposes of this demonstration). 4) maximum output current, i out (we will design for 10a) switching frequency determines the trade-off between size and efficiency. increased frequency increases the switching losses in the mosfets, since losses are a function of vin 2 . knowing the maximum input voltage and budget for mosfet switches usually dictates where the design ends up. it is recommended that the two outputs are designed to operate at frequencies approximately 25% apart to avoid any possible interaction. it is also recommended that the higher frequency output is the lower output voltage output, since this will tend to have lower output ripple and tighter specifications. the default r ton values of 1m ? and 649k ? are suggested as a starting point, but these are not set in stone. the first thing to do is to calculate the on-time, t on , at v in(min) and v in(max) , since this depends only upon v in , v out and r ton . for v out < 3.3v: () s 10 50 v v 10 37 r 10 3 . 3 t 9 ) min ( in out 3 ton 12 ) min ( vin _ on ? ? ? + ? ? ? ? ? ? ? ? ? ? + ? ? = and () s 10 50 v v 10 37 r 10 3 . 3 t 9 ) max ( in out 3 ton 12 ) max ( vin _ on ? ? ? + ? ? ? ? ? ? ? ? ? ? + ? ? = from these values of t on we can calculate the nominal switching frequency as follows: () hz t v v f ) min ( vin _ on ) min ( in out ) min ( vin _ sw ? = and () hz t v v f ) max ( vin _ on ) max ( in out ) max ( vin _ sw ? = t on is generated by a one-shot comparator that samples v in via r ton , converting this to a current. this current is used to charge an internal 3.3pf capacitor to v out . the equations above reflect this along with any internal com- ponents or delays that influence t on . for our ddr2 vddq example we select r ton = 1m ? : t on_vin(min) = 871ns and t on_vin(max) = 350ns f sw_vin(min) = 275khz and f sw_vin(max) = 251khz now that we know t on we can calculate suitable values for the inductor. to do this we select an acceptable inductor ripple current. the calculations below assume 50% of i out which will give us a starting place. () () h i 5 . 0 t v v l out ) min ( vin _ on out ) min ( in ) min ( vin ? ? ? = and () () h i 5 . 0 t v v l out ) max ( vin _ on out ) max ( in ) max ( vin ? ? ? = for our ddr2 vddq example: l vin(min) = 1h and l vin(max) = 1.3h we will select an inductor value of 2.4h to reduce the ripple current, which can be calculated as follows: () p p ) min ( vin _ on out ) min ( in ) min ( vin _ ripple a l t v v i ? ? ? = and () p p ) max ( vin _ on out ) max ( in ) max ( vin _ ripple a l t v v i ? ? ? =
14 ? 2006 semtech corp. www.semtech.com sc1486a power management application information (cont.) design procedure (cont.) for our ddr2 vddq example: i ripple_vin(min) = 2.07a p-p and i ripple_vin(max) = 2.73a p-p from this we can calculate the minimum inductor current rating for normal operation: ) min ( ) max ( vin _ ripple ) max ( out ) min ( inductor a 2 i i i + = for our ddr2 vddq example: i inductor(min) = 11.4a (min) next we will calculate the maximum output capacitor equivalent series resistance (esr). this is determined by calculating the remaining static and transient tolerance allowances. then the maximum esr is the smaller of the calculated static esr (r esr_st(max) ) and transient esr (r esr_tr(max) ): () ohms i 2 err err r ) max ( vin _ ripple dc st ) max ( st _ esr ? ? = where err st is the static output tolerance and err dc is the dc error. the dc error will be 1% plus the tolerance of the feedback resistors, thus 2% total for 1% feed- back resistors. for our ddr2 vddq example: err st = 100mv and err dc = 36mv, therefore r esr_st(max) = 47m ? () ohms 2 i i err err r ) max ( vin _ ripple out dc tr ) max ( tr _ esr ? ? ? ? ? ? ? ? + ? = where err tr is the transient output tolerance. note that this calculation assumes that the worst case load tran- sient is full load. for half of full load, divide the i out term by 2. for our ddr2 vddq example: err tr = 144mv and err dc = 36mv, therefore r esr_tr(max) = 9.5m ? for a full 10a load transient we will select a value of 12.5m ? maximum for our design, which would be achieved by using two 25m ? output capacitors in parallel. note that for constant-on converters there is a minimum esr requirement for stability which can be calculated as follows: sw out ) min ( esr f c 2 3 r ? ? ? = this criteria should be checked once the output capacitance has been determined. now that we know the output esr we can calculate the output ripple voltage: p p ) max ( vin _ ripple esr ) max ( vin _ ripple v i r v ? ? = and p p ) min ( vin _ ripple esr ) min ( vin _ ripple v i r v ? ? = for our ddr2 vddq example: v ripple_vin(max) = 34mv p-p and v ripple_vin(min) = 26mv p-p note that in order for the device to regulate in a controlled manner, the ripple content at the feedback pin, v fb , should be approximately 15mv p-p at minimum v in , and worst case no smaller than 10mv p-p . if v ripple_vin(min) is less than 15mv p-p the above component values should be revisited in order to improve this. quite often a small capacitor, c top , is required in parallel with the top feedback resistor, r top , in order to ensure that v fb is large enough. c top should not be greater than 100pf. the value of c top can be calculated as follows, where r bot is the bottom feedback resistor. firstly calculating the value of z top required: () ohms 015 . 0 v 015 . 0 r z ) min ( vin _ ripple bot top ? ? = secondly calculating the value of c top required to achieve this:
15 ? 2006 semtech corp. www.semtech.com sc1486a power management application information (cont.) design procedure (cont.) f f 2 r 1 z 1 c ) min ( vin _ sw top top top ? ? ? ? ? ? ? ? ? ? ? = for our ddr2 vddq example we will use r top = 45.3k ? and r bot = 17.4k ? , therefore: z top = 12.8k ? and c top = 32pf we will select a value of c top = 27pf. calculating the value of v fb based upon the selected c top : p p top ) min ( vin _ sw top bot bot ) min ( vin _ ripple ) min ( vin _ fb v c f 2 r 1 1 r r v v ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + + ? = for our ddr2 vddq example: v fb_vin(min) = 14.2mv p-p - good next we need to calculate the minimum output capaci- tance required to ensure that the output voltage does not exceed the transient maximum limit, poslim tr , start- ing from the actual static maximum, v out_st_pos , when a load release occurs: v err v v dc out pos _ st _ out + = for our ddr2 vddq example: v out_st_pos = 1.836v v tol v poslim tr out tr ? = where tol tr is the transient tolerance. for our ddr2 vddq example: poslim tr = 1.944v the minimum output capacitance is calculated as follows: () f v poslim 2 i i l c 2 pos _ st _ out 2 tr 2 ) max ( vin _ ripple out ) min ( out ? ? ? ? ? ? ? ? ? + ? = this calculation assumes the absolute worst case condition of a full-load to no load step transient occurring when the inductor current is at its highest. the capacitance required for smaller transient steps my be calculated by substituting the desired current for the i out term. for our ddr2 vddq example: c out(min) = 760f. we will select 660f, using two 330f, 25m ? capacitors in parallel. next we calculate the rms input ripple current, which is largest at the minimum battery voltage: () rms min _ in out out ) min ( in out ) rms ( in a v i v v v i ? ? ? = for our ddr2 vddq example: i in(rms) = 4.27a rms input capacitors should be selected with sufficient ripple current rating for this rms current, for example a 10f, 1210 size, 25v ceramic capacitor can handle a little more than 2a rms . refer to manufacturer?s data sheets. finally, we calculate the current limit resistor value. as described in the current limit section, the current limit looks at the ?valley current?, which is the average output current minus half the ripple current. we use the maximum room temperature specification for mosfet r ds(on) at v gs = 4.5v for purposes of this calculation: a 2 i i i ) min ( vin _ ripple out valley ? = the ripple at low battery voltage is used because we want to make sure that current limit does not occur under normal operating conditions.
16 ? 2006 semtech corp. www.semtech.com sc1486a power management application information (cont.) design procedure (cont.) () ohms 10 10 4 . 1 r 2 . 1 i r 6 ) on ( ds valley ilim ? ? ? ? ? = for our ddr2 vddq example: i valley = 8.97a and r ilim = 13.6k ? we select the next lowest 1% resistor value: 13.3k ? thermal considerations the junction temperature of the device may be calculated as follows: c p t t ja d a j ? + = where: t a = ambient temperature (c) p d = power dissipation in (w) ja = thermal impedance junction to ambient from absolute maximum ratings (c/w) the power dissipation may be calculated as follows: () w f q v i vcca 2 p g g vcca d ? ? + ? ? = where: vcca = chip supply voltage (v) i vcca = operating current (a) v g = gate drive voltage, typically 5v (v) q g = fet gate charge, from the fet datasheet (c) f = switching frequency (khz) inserting the following values as an example: t a = 85c ja = 37c/w vcca = 5v i vcca = 1100a (data sheet maximum) v g = 5v q g = 60nc f = 300khz (enter the higher of the two set frequencies here) gives us: () c 98 70 10 300 10 60 5 10 1100 5 2 85 t 3 9 6 j = ? ? ? ? ? + ? ? ? + = ? ? as can be seen, the heating effects due to internal power dissipation are minor, thus requiring no special consider- ation thermally during layout.
17 ? 2006 semtech corp. www.semtech.com sc1486a power management application information (cont.) layout guidelines one (or more) ground planes is/are recommended to minimize the effect of switching noise and copper losses, and maximize heat dissipation. the ic ground references, vssa1 and vssa2, should be kept separate from power ground. all components that are referenced to them should connect to them locally at the chip. vssa1 and vssa2 should connect to power ground at their respective output capacitors only. feedback traces must be kept far away from noise sources such as switching nodes, inductors and gate drives. route feedback traces with their respective vssas as a differential pair from the output capacitor back to the chip. run them in a ?quiet layer? if possible. chip decoupling capacitors (vddp, vcca) should be located next to the pins and connected directly to them on the same side. power sections should connect directly to the ground plane(s) using multiple vias as required for current handling (including the chip power ground connections). power components should be placed to minimize loops and reduce losses. make all the connections on one side of the pcb using wide copper filled areas if possible. do not use ?minimum? land patterns for power components. minimize trace lengths between the gate drivers and the gates of the mosfets to reduce parasitic impedances (and mosfet switching losses), the low-side mosfet is most critical. maintain a length to width ratio of <20:1 for gate drive signals. use multiple vias as required by current handling requirement (and to reduce parasitics) if routed on more than one layer current sense connections must always be made using kelvin connections to ensure an accurate signal. we will examine the sc1486a ddr2 reference design used in the design procedure section while explaining the layout guidelines in more detail. vssa1 c11 0u1 c8 1u 0402 c16 0u1 0402 r2 10r vcca1 c2 0u1/25v + c15 220u/25m + c14 330u/25m r13 17k4 c10 0u1 r8 0r r10 45k3 0603 0603 c9 1u 0402 ton2 pgood2 r1 10r c7 2n2/50v r9 10k0 q1 fds6982s 4 1 2 3 5 6 7 8 u1 sc1486a 3 1 23 6 7 5 4 22 27 24 26 25 28 17 15 9 20 21 19 18 13 12 8 10 11 14 2 16 vddp1 pgnd1 ton1 dh1 bst1 lx1 ilim1 en/psv1 pgd1 vout1 fb1 vcca1 vssa1 vddp2 pgnd2 ton2 dh2 bst2 lx2 ilim2 pgd2 fb2 refin refout vcca2 vssa2 dl1 dl2 r14 470k r3 1m 7343 r6 4k32 0603 1210 0402 vcca1 r7 0r pwr_src pgd2 ton1 0402 sod 0402 r5 13k3 refout q2 irf7811av 1 2 3 4 5 6 7 8 s s s g d d d d d2 0402 c19 0u1 c6 0u1/25v 323 pgood1 0402 0603 0.9v 0.9v, 1.5a vcca2 l2 3u9 r15 470k 0402 vcca1 0402 0402 0603 c23 1n c1 2n2/50v 0402 0603 vcca2 0402 c20 1n 0402 1210 5vsus 1.8v 0402 c12 0u1 0402 1.8v, 10a c3 10u/25v q3 fds6676s 1 2 3 4 5 6 7 8 s s s g d d d d vssa2 0603 0603 0402 1.8v sod 0402 + c13 330u/25m 7343 c22 1u 5vsus pgd1 pwr_src c18 1u 0402 0402 l1 2u4 d1 r12 10k0 r4 649k 0402 7343 323 c21 1u 0402 c17 27p 0603 0402 r11 10r 1210 c4 10u/25v 5vrun c5 10u/25v figure 4: ddr2 reference design and layout example sample ddr2 design using sc1486a pwr_src = 7.5v to 20.5v vddq = 1.8v @ 10a vtt = 0.9v @ 1.5a schematic is drawn to emphasize required grounding scheme
18 ? 2006 semtech corp. www.semtech.com sc1486a power management application information (cont.) layout guidelines (cont.) 5vsus 0402 c1 2n2/50v q2 irf7811av 1 2 3 4 5 6 7 8 s s s g d d d d sod 0402 7343 0603 0402 323 r5 13k3 c2 0u1/25v 0603 r3 1m r13 17k4 c10 0u1 d1 0402 r10 45k3 1210 + c14 330u/25m c20 1n 1.8v 0402 l1 2u4 5vsus c17 27p pgood1 vcca1 0402 r1 10r vcca1 0603 0603 vcca1 r7 0r 0402 c3 10u/25v u1 sc1486a 3 1 23 6 7 5 4 22 27 24 26 25 28 17 15 9 20 21 19 18 13 12 8 10 11 14 2 16 vddp1 pgnd1 ton1 dh1 bst1 lx1 ilim1 en/psv1 pgd1 vout1 fb1 vcca1 vssa1 vddp2 pgnd2 ton2 dh2 bst2 lx2 ilim2 pgd2 fb2 refin refout vcca2 vssa2 dl1 dl2 c4 10u/25v c21 1u ton1 c8 1u 0402 0402 7343 + c13 330u/25m pgd1 r14 470k q3 fds6676s 1 2 3 4 5 6 7 8 s s s g d d d d vssa1 0402 0402 1.8v, 10a pwr_src 1210 c12 0u1 figure 5: vddq side detail note r7 is present to facilitate isolation of power ground and vssa1 during layout 0603 pwr_src l2 3u9 0.9v 0402 r2 10r d2 0402 c9 1u 0402 1.8v r11 10r c19 0u1 7343 + c15 220u/25m r9 10k0 c6 0u1/25v 0603 0603 c16 0u1 pgd2 c11 0u1 u1 sc1486a 3 1 23 6 7 5 4 22 27 24 26 25 28 17 15 9 20 21 19 18 13 12 8 10 11 14 2 16 vddp1 pgnd1 ton1 dh1 bst1 lx1 ilim1 en/psv1 pgd1 vout1 fb1 vcca1 vssa1 vddp2 pgnd2 ton2 dh2 bst2 lx2 ilim2 pgd2 fb2 refin refout vcca2 vssa2 dl1 dl2 q1 fds6982s 4 1 2 3 5 6 7 8 c5 10u/25v 0402 0402 0402 0402 r4 649k r8 0r c22 1u r15 470k sod 5vsus 0.9v, 1.5a refout 5vrun 1210 c7 2n2/50v 0603 0402 323 0402 ton2 c23 1n 0603 0402 pgood2 vssa2 c18 1u vcca2 vcca2 r12 10k0 r6 4k32 0402 0402 figure 6: vtt side detail note r8 is present to facilitate isolation of power ground and vssa2 during layout
19 ? 2006 semtech corp. www.semtech.com sc1486a power management application information (cont.) layout guidelines (cont.) the layout can be considered in two parts, the control section referenced to vssa1/2 and the power section. looking at the control section first, locate all components referenced to vssa1/2 on the schematic and place these components at the chip. connect vssa1 and vssa2 using either a wide (>0.020?) trace or a copper pour if room allows. very little current flows in the chip ground therefore large areas of copper are not needed. u1 sc1486a 3 1 23 6 7 5 4 22 27 24 26 25 28 17 15 9 20 21 19 18 13 12 8 10 11 14 2 16 vddp1 pgnd1 ton1 dh1 bst1 lx1 ilim1 en/psv1 pgd1 vout1 fb1 vcca1 vssa1 vddp2 pgnd2 ton2 dh2 bst2 lx2 ilim2 pgd2 fb2 refin refout vcca2 vssa2 dl1 dl2 pwr_src pwr_src 5vsus vcca2 5vrun r10 45k3 c21 1u 0402 c18 1u vcca1 pgd1 refout 0402 c9 1u r2 10r 0402 r3 1m 0603 0402 1.8v c20 1n 0603 vcca2 0402 c22 1u 0402 c17 27p 0402 0402 1.8v c8 1u r9 10k0 0402 vcca1 ton1 r1 10r r11 10r 0.9v r4 649k 0603 c23 1n r13 17k4 0402 vssa2 0603 c19 0u1 vssa1 ton2 r12 10k0 0603 vcca1 0402 pgd2 0402 figure 7: components connected to vssa1 and vssa2 figure 8: examplevssa copper pours (left) and 0.020? traces (right)
20 ? 2006 semtech corp. www.semtech.com sc1486a power management application information (cont.) layout guidelines (cont.) in figure 8 on page 19, all components referenced to vssa1 and vssa2 have been placed and have been connected using copper pours (left) or 0.020? traces (right). note that there are two separate copper pours or traces, one for vssa1 and one for vssa2. decoupling capacitors c2 and c22 are as close as possible to their pins, as are vddp decoupling capacitors c8 and c9. c8 and c9 should connect to the ground plane using two vias each. 0603 0402 r13 17k4 vcca1 1.8v 0402 0402 1.8v, 10a route as differential pair to output capacitors 0402 r7 0r 0402 c20 1n + c13 330u/25m vssa1 c21 1u r10 45k3 7343 7343 c17 27p c12 0u1 u1 sc1486a 3 1 23 6 7 5 4 22 27 24 26 25 28 17 15 9 20 21 19 18 13 12 8 10 11 14 2 16 vddp1 pgnd1 ton1 dh1 bst1 lx1 ilim1 en/psv1 pgd1 vout1 fb1 vcca1 vssa1 vddp2 pgnd2 ton2 dh2 bst2 lx2 ilim2 pgd2 fb2 refin refout vcca2 vssa2 dl1 dl2 0402 + c14 330u/25m 0402 u1 sc1486a 3 1 23 6 7 5 4 22 27 24 26 25 28 17 15 9 20 21 19 18 13 12 8 10 11 14 2 16 vddp1 pgnd1 ton1 dh1 bst1 lx1 ilim1 en/psv1 pgd1 vout1 fb1 vcca1 vssa1 vddp2 pgnd2 ton2 dh2 bst2 lx2 ilim2 pgd2 fb2 refin refout vcca2 vssa2 dl1 dl2 vcca2 0402 vssa2 0603 r8 0r route as differential pair to output capacitors 0.9v + c15 220u/25m 0.9v, 1.5a c22 1u 7343 c16 0u1 figure 9: differential routing of feedback and ground reference traces
21 ? 2006 semtech corp. www.semtech.com sc1486a power management application information (cont.) layout guidelines (cont.) next, looking at the power section, the schematics in figures 10 and 11 below show the power sections for vddq and vtt: + c13 330u/25m q2 irf7811av 1 2 3 4 5 6 7 8 s s s g d d d d 1210 q3 fds6676s 1 2 3 4 5 6 7 8 s s s g d d d d 0402 0402 1210 + c14 330u/25m 7343 l1 2u4 7343 c2 0u1/25v 0603 c1 2n2/50v c3 10u/25v 0402 c4 10u/25v c12 0u1 1.8v, 10a r7 0r 0402 r8 0r l2 3u9 1210 0603 c6 0u1/25v 0603 0402 c7 2n2/50v c5 10u/25v c16 0u1 + c15 220u/25m 0402 7343 0.9v, 1.5a q1 fds6982s 4 1 2 3 5 6 7 8 figure 10: vddq power section figure 11: vtt power section the highest di/dts occur in the input loops (see figures 12 and 13 below) and thus these should be kept as small as possible. figure 12: vddq input loop figure 13: vtt input loop c3 10u/25v 0603 c1 2n2/50v 1210 q2 irf7811av 1 2 3 4 5 6 7 8 s s s g d d d d c2 0u1/25v c4 10u/25v 0402 q3 fds6676s 1 2 3 4 5 6 7 8 s s s gd d d d 1210 0402 c6 0u1/25v 0603 c7 2n2/50v q1 fds6982s 4 1 2 3 5 6 7 8 c5 10u/25v 1210 the input capacitors should be placed with the highest frequency capacitors closest to the loop to reduce emi. use large copper pours to minimize losses and parasitics. see figures 14 and 15 below for examples. figure 14: vddq power component placement and copper pours figure 15: vtt power component placement and copper pours
22 ? 2006 semtech corp. www.semtech.com sc1486a power management layout guidelines (cont.) key points for the power section: 1) there should be a very small input loop, well decoupled. 2) the phase node should be a large copper pour, but compact since this is the noisiest node. 3) input power ground and output power ground should not connect directly, but through the ground planes instead. 4) the two outputs should not share their input capacitors, and these should have separate pwr_src and pgnd (component-side) copper pours. 5) the two output inductors should not be placed adjacent to each other to avoid crosstalk. 6) notice in figures 10 and 11 on the previous page placement of 0 ? resistor at the bottom of the output capacitor to connect to vssa1/2 for each output. connecting the control and power sections should be accomplished as follows (see figure 16 below): 1) route vssa1/2 and their related feedback traces as differential pairs routed in a ?quiet? layer away from noise sources. 2) route dl, dh and lx (low side fet gate drive, high side fet gate drive and phase node) to chip using wide traces with multiple vias if using more than one layer. these connections to be as short as possible for loop minimization, with a length to width ratio less than 20:1 to minimize impedance. dl is the most critical gate drive, with power ground as its return path. lx is the noisiest node in the circuit, switching between pwr_src and ground at high frequencies, thus should be kept as short as practical. dh has lx as its return path. 3) bst is also a noisy node and should be kept as short as possible. 4) connect pgnd pins on the chip directly to the vddp decoupling capacitor and then drop vias directly to the ground plane. q3 fds6676s 1 2 3 4 5 6 7 8 s s s g d d d d u1 sc1486a 3 1 23 6 7 5 4 22 27 24 26 25 28 17 15 9 20 21 19 18 13 12 8 10 11 14 2 16 vddp1 pgnd1 ton1 dh1 bst1 lx1 ilim1 en/psv1 pgd1 vout1 fb1 vcca1 vssa1 vddp2 pgnd2 ton2 dh2 bst2 lx2 ilim2 pgd2 fb2 refin refout vcca2 vssa2 dl1 dl2 phase nodes ( black ) to be copper islands ( preferred ) or wide copper t r gate drive traces (red) and phase node traces (blue) to be wide copper traces ( l:w < 20:1 ) and as short as possible, with dl the most critical q1 fds6982s 4 1 2 3 5 6 7 8 l2 3u9 l1 2u4 q2 irf7811av 1 2 3 4 5 6 7 8 s s s g d d d d figure 16: connecting control and power sections application information (cont.)
23 ? 2006 semtech corp. www.semtech.com sc1486a power management typical characteristics vddq efficiency (power save mode) vs. output current vs. input voltage vddq output voltage (power save mode) vs. output current vs. input voltage vddq efficiency (continuous conduction mode) vs. output current vs. input voltage vddq output voltage (continuous conduction mode) vs. output current vs. input voltage vtt efficiency vs. output current vs. input voltage vtt output voltage vs. output current vs. input voltage 50 55 60 65 70 75 80 85 90 95 100 012345678910 i out (a) efficiency (%) v bat = 20v v bat = 8v 1.780 1.784 1.788 1.792 1.796 1.800 1.804 1.808 1.812 1.816 1.820 012345678910 i out (a) v out (v) v bat = 20v v bat = 8v 50 55 60 65 70 75 80 85 90 95 100 012345678910 i out (a) efficiency (%) v bat = 20v v bat = 8v 1.780 1.784 1.788 1.792 1.796 1.800 1.804 1.808 1.812 1.816 1.820 012345678910 i out (a) v out (v) v bat = 20v v bat = 8v 50 55 60 65 70 75 80 85 90 95 100 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 i out (a) efficiency (%) v bat = 20v v bat = 8v 0.890 0.892 0.894 0.896 0.898 0.900 0.902 0.904 0.906 0.908 0.910 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 i out (a) v out (v) v bat = 20v v bat = 8v refin = 0.9v please refer to figure 4 on page 17 for test schematic
24 ? 2006 semtech corp. www.semtech.com sc1486a power management vddq switching frequency (continuous conduction mode) vs. output current vs. input voltage typical characteristics (cont.) vtt switching frequency (continuous conduction mode) vs. output current vs. input voltage 200 225 250 275 300 325 350 012345678910 i out (a) f sw (khz) v bat = 8v v bat = 20v 250 275 300 325 350 375 400 425 450 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 i out (a) f sw (khz) v bat = 20v v bat = 8v refin = 0.9v vddq switching frequency (power save mode) vs. output current vs. input voltage 0 50 100 150 200 250 300 350 012345678910 i out (a) f sw (khz) v bat = 20v v bat = 8v please refer to figure 4 on page 17 for test schematic
25 ? 2006 semtech corp. www.semtech.com sc1486a power management typical characteristics (cont.) vddq load transient response, continuous conduction mode, 0a to 10a to 0a trace 1: vddq, 100mv/div., ac coupled trace 2: lx, 10v/div trace 3: not connected trace 4: load current, 10a/div timebase: 40s/div. please refer to figure 4 on page 17 for test schematic vddq load transient response, continuous conduction mode, 0a to 10a zoomed vddq load transient response, continuous conduction mode, 10a to 0a zoomed trace 1: vddq, 50mv/div., ac coupled trace 2: lx, 10v/div trace 3: not connected trace 4: load current, 10a/div timebase: 10s/div. trace 1: vddq, 20mv/div., ac coupled trace 2: lx, 10v/div trace 3: not connected trace 4: load current, 10a/div timebase: 10s/div.
26 ? 2006 semtech corp. www.semtech.com sc1486a power management typical characteristics (cont.) vddq load transient response, power save mode, 0a to 10a to 0a trace 1: vddq, 100mv/div., ac coupled trace 2: lx, 10v/div trace 3: not connected trace 4: load current, 10a/div timebase: 40s/div. please refer to figure 4 on page 17 for test schematic vddq load transient response, power save mode, 0a to 10a zoomed vddq load transient response, power save mode, 10a to 0a zoomed trace 1: vddq, 50mv/div., ac coupled trace 2: lx, 10v/div trace 3: not connected trace 4: load current, 10a/div timebase: 10s/div. trace 1: vddq, 20mv/div., ac coupled trace 2: lx, 10v/div trace 3: not connected trace 4: load current, 10a/div timebase: 10s/div.
27 ? 2006 semtech corp. www.semtech.com sc1486a power management typical characteristics (cont.) vtt load transient response, 0a to 1.5a to 0a trace 1: vtt, 50mv/div., ac coupled trace 2: lx, 10v/div trace 3: not connected trace 4: load current, 1a/div timebase: 40s/div. please refer to figure 4 on page 17 for test schematic vtt load transient response, 0a to 1.5a zoomed vtt load transient response, 1.5a to 0a zoomed trace 1: vtt, 20mv/div., ac coupled trace 2: lx, 10v/div trace 3: not connected trace 4: load current, 1a/div timebase: 10s/div. trace 1: vtt, 20mv/div., ac coupled trace 2: lx, 10v/div trace 3: not connected trace 4: load current, 1a/div timebase: 10s/div.
28 ? 2006 semtech corp. www.semtech.com sc1486a power management typical characteristics (cont.) startup (ccm), en/psv1 going 0v to floating trace 1: vddq, 1v/div. trace 2: vtt, 0.5v/div trace 3: refout, 0.5v/div trace 4: en/psv1, 2v/div. timebase: 2ms/div. please refer to figure 4 on page 17 for test schematic startup (ccm) showing pgd1 and pgd2 trace 1: vddq, 1v/div. trace 2: vtt, 0.5v/div. trace 3: pgd1, 5v/div. trace 4: pgd2, 5v/div timebase: 2ms/div.
29 ? 2006 semtech corp. www.semtech.com sc1486a power management outline drawing - tssop-28 n a a2 a1 bxn e1 .378 9.60 .386 9.70 9.80 plane bbb c a-b d ccc c dimensions "e1" and "d" do not include mold flash, protrusions 3. or gate burrs. datums and to be determined at datum plane controlling dimensions are in millimeters (angles in degrees). -b- notes: 1. 2. -a- -h- side view a b c d e h e/2 (.039) .008 - .004 .024 - - - - 0 l (l1) c 01 gage plane see detail detail a a 0.25 .026 bsc .252 bsc 28 .004 .169 .173 .007 - 28 0.10 0.65 bsc 6.40 bsc 4.40 - .177 4.30 .012 0.19 4.50 0.30 .382 2x n/2 tips seating aaa c e/2 indicator pin 1 2x 2 13 .018 .003 .031 .002 - 8 0 0.20 0.10 - 8 0.45 0.09 0.80 0.05 .030 .007 .047 .042 .006 - 0.60 (1.0) - 0.75 0.20 - - - 1.20 1.05 0.15 d reference jedec std mo-153, variation ae. 4. inches b n bbb aaa ccc 01 e1 e l l1 e d c dim a1 a2 a min max millimeters dimensions min max nom nom e
30 ? 2006 semtech corp. www.semtech.com sc1486a power management semtech corporation power management products division 200 flynn road, camarillo, ca 93012 phone: (805)498-2111 fax (805)498-3804 contact information land pattern - tssop-28 (.222) (5.65) z g y p (c) 4.10 .161 0.65 .026 0.40 .016 1.55 .061 7.20 .283 x inches dimensions z p y x dim c g millimeters this land pattern is for reference purposes only. consult your manufacturing group to ensure your company's manufacturing guidelines are met. notes: 1.

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